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Nanotechnology Competition Announced
Nanotech Briefs, the digital magazine from the publishers of NASA Tech Briefs, has announced the 4th Annual Nano 50™. The Nano 50 is the ultimate list of the top 50 technologies, products and innovators that have significantly impacted, or will impact, key nanotechnology commercial markets from automotive and electronics to biomedical and materials. The Nano 50 represents the best of the best – the most innovative people and design ideas that will revolutionize nanotechnology in the near-term and beyond. Entries will be judged on four criteria: realized or anticipated impact on the commercial market, benefits and near-term practical applications, novelty and accomplishments in the nanotechnology field. Entries must fit within one of three categories:
- Technology - A novel engineering method, process or research breakthrough in nanotechnology that has or is anticipated to have a significant impact in one or more application areas.
- Product - A unique product that incorporates nanotechnology in its design and/or operation, with significant current or near-term applications in one or more commercial market sectors.
- Innovator - An individual recognized as a leader in a specific area of nanotechnology, with a significant background of accomplishments in advancing the state of the art in nanotechnology.
The top 50 entries will receive an award, presented at an awards dinner to be held at the National Nano Engineering Conference in the fall of 2008 and be featured on the Nanotech Briefs web site. Entries must be received by 11:59 p.m. ET on Friday, 21 March 2008. Learn more
World’s Fastest Embedded Dram Technology Claimed
The world's fastest circuit technology for embedded DRAM for System LSI—833 megahertz at 32 megabytes density—has been developed by Toshiba Corporation. According to the Tokyo electronics giant, the technology will be applied to graphic processing LSI. To achieve high-speed operation, Toshiba said it applied a "pseudo two port system," a technology that virtually divides the overall memory into two and then reads and writes data in parallel and alternately. System LSI will be used in next-generation, high-end digital consumer products, game applications, mobile phones, projectors and other image-related applications that require high speed transfer of large volumes of data. Toshiba is also expected to apply the technology to its leading edge 65 nanometer system LSI process. Read more
Learn more about embedded DRAM technology in IEEE Xplore®
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University and Industrial Electronics Firm Partner on High-Frequency Circuit
The world's highest frequency circuit made with complementary metal oxide silicon technology has been developed by engineers from the University of Florida and Texas Instruments. According to researchers, the circuit is a breakthrough that could slash the price of detectors useful in medicine, environmental monitoring and military applications. A 410 gigahertz circuit—approximately 60 gigahertz higher than a previous record set using alternative and more expensive indium phosphide technology—was demonstrated in the laboratory at the university. Engineers say Texas Instrument’s advanced manufacturing technology serves as the foundation for the new circuit. The technology could reduce the cost of detection and imaging systems by a factor of 100 or more. Read more
Learn more about high frequency circuits in IEEE Xplore®
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International Symposium on Physical Design
Sponsored by the IEEE Circuits and Systems Society, the 2008 International Symposium on Physical Design (ISPD 2008) will provide a premier forum to exchange ideas and promote research on critical areas related to the physical design of VLSI systems. All aspects of physical design, including its interactions with architecture, behavioral- and logic-level synthesis and back-end performance analysis and verification are within the scope of the symposium. Target domains include semi-custom and full-custom IC, regular fabrics, FPGA and systems-on-chip/systems-in-package. ISPD 2008 will take place 13-16 April 2008 in Portland, Oregon, USA. Learn more
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Guides for Nanotechnology Industry Published
BSI British Standards, the United Kingdom’s national standards organization, has published nine documents for nanotechnology terminology. The documents will provide guidance for UK industries; support worker, public and environmental safety; and establish a course of action for commercialization and procurement. The publication anticipates a worldwide market for nanotechnology-enabled products exceeding $1 trillion a year by 2015. Nanotechnologies are already used in medicine, green technology and in more than 500 consumer products. BSI British Standards drew on industry expertise to create common definitions for nano-related products and guidance on labeling, safe handling and materials specification. Read more
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Human Body Heat Could Power Energy-Efficient Chip
A new chip design that consumes 10 times less power than traditional chips and can run implantable medical devices using human body heat as an energy source was recently unveiled by Massachusetts Institute of Technology researchers, who say it will take approximately five years for the chips to be used in production devices. The chip's improved energy efficiency is achieved by making it work at about 0.3 volts, as opposed to the current 1 volt standard, which gives it the complexity to handle more functions and increases battery life. The voltage required by a device depends on what it is doing; if the chip is idle, 0.3 volts would be enough to operate it, but if the device is doing something that requires high speed, the chip would need to use more voltage. The chip is designed to scale between higher and lower voltages, while additional transistors within the design will make it harder to disturb data within the cell when a read operation is performed. Read more
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Electrically Trimmable Passive Resistor Debuts
The world's first analog integrated circuit to incorporate electrically adjustable passive resistors was developed by Microbridge Technologies Inc. The trimmable Wheatstone bridge for piezoelectric sensors is made possible with Microbridge’s patented "rejustor" technology based on microelectromechanical systems. Microbridge says its rejustor is designed as an inexpensive alternative to the expensive, laser-trimmed resistors and intricate active circuitry now used to compensate for inaccuracies introduced while manufacturing, assembling and packaging analog circuits. Its trimmable Wheatstone bridge can compensate for variation in both offset and sensitivity, as well as for temperature-induced offset and sensitivity drift. Read more
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Researchers Develop Circuits with Copper Connections
Researchers at Georgia Tech’s School of Chemical and Biomolecular Engineering have developed copper interconnections in next-generation integrated circuits. The interconnections are expected to boost the efficiency of connections between chips and external circuitry like a motherboard. Paul Kohl, Thomas L. Gossage chair and Regents Professor at the school, explained that the vertical connections between chips and boards are currently formed by melting tin solder between the two pieces and adding glue to hold everything together. Research performed at the school shows that replacing the solder ball connections with copper pillars creates stronger connections and the ability to create more connections. "Circuitry and computer chips are made with copper lines on them, so we thought we should make the connection between the two with copper also," said Kohl. While solder and copper can both tolerate misalignment between two pieces being connected, copper is more conductive and creates a stronger bond. Read more
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European Project Strives for Heterogeneous Channels
A European project to create dual-channel CMOS was recently announced by the European Commission’s 7th Framework Program (FP7) in Information and Communication Technologies. The goal of the Duallogic program will be the co-integration of germanium PMOS and III-V NMOS, “side-by-side on a silicon substrate to demonstrate for the first time a dual-channel CMOS technology.” The project will include European IC and equipment manufacturers, technology development laboratories, research centers and universities from eight different countries. Seeking to create a “scalable and manufacturable” process employing a silicon-compatible process in a 65 nm technology on a 200 mm pilot line, researchers expect to determine if a dual-channel CMOS approach is a viable option for CMOS beyond 22 nm by the end of 2009. Read more
Learn more about dual-channel CMOS in IEEE Xplore®
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New Single-Chip Solution Introduced
Qualcomm, a developer of advanced wireless technologies and data solutions, has introduced a new single-chip solution. Combining rich multimedia, power-saving technology and broadband data speeds for the next generation of mainstream handsets, the Qualcomm Single Chip (QSC) QSC6295 leverages 45 nanometer CMOS process technology. Steve Mollenkopf, senior vice president of product management at Qualcomm, explained that the QSC6295 integrates baseband, multimedia processing and radio functionality into a single chip, enabling significant cost and time-to-market advantages to help drive wireless broadband and 3G adoption in mass markets. The QSC6295 is scheduled to sample in the first quarter of 2009. Read more
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Wipro to Provide Chip Design Services to NEC Electronics
Indian IT company Wipro Technologies has been selected for semiconductor design services by Japanese chip major NEC Electronics. “Wipro has set up a dedicated engineering development center to provide chip design services and support activities. The center will offer front-end and backend design services and IP (intellectual property) to NEC for application-specified integrated circuits (ASICs) and micro-controllers in digital consumer and automotive areas,” NEC Electronics president and CEO Toshio Nakajima told reporters. Sudip Nandy, Wipro Technologies president for telecom and product engineering solutions, said the software company would leverage its vast VLSI (very large system integration) expertise with its in-house design methodology to deliver advance designs to NEC Electronics. With a team of 25 engineers initially, Wipro will work on various designs ranging from 150 nanometers (nm), 130 nm and 55 nm for NEC Electronics. Read more
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