What's New at IEEE
What's New @ IEEE in Circuits March 19, 2008
INSIDE THIS ISSUE
Circuits, Transistors and Nanotech Top MIT’s Emerging Technology List
Call for Proposals: Real World Engineering Projects
Chipmaker Debuts 45-NM Sets, Hybrid Graphics
Chip Makers Tailoring Products for Local Market
Circuits and Systems Symposium
Self-Assembling Organic Circuits Tested
Join IEEE for a Free Webinar on Photonic Integrated Circuits
IBM and Hitachi Team Up to Advance Chip Research
E-Noses Sample the Sweet Smell of Success
New Technology for Random Numbers Generated
Nano-Printing Technology May Open Way to the Ultra-Small
“If everyone is thinking alike then somebody isn’t thinking.”
~ George S. Patton, Jr.
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Circuits, Transistors and Nanotech Top MIT’s Emerging Technology List
Massachusetts Institute of Technology, USA, has named its picks for the top 10 emerging technologies for 2008. The list, which covers a wide variety of discipline areas from physics and chemistry to medicine and biology, has several technologies that bear directly on information technology. Nano radios, tiny radios built out of carbon nanotubes, should have a big impact on everything from medical diagnostics to computer interfaces and personal communications devices. Graphene transistors are expected to make Moore’s Law hold a bit longer with their capability of running orders of magnitude faster than silicon based circuits while generating far less heat and conducting it away more rapidly.  Probabilistic chips that get “close enough” rather than exactly correct can save power and heat generation, also helping out Moore’s Law in some applications where precision is not of paramount importance such as scientific computer modeling and multimedia processing. Read more 
Learn more about transistors in IEEE Xplore®

 

 

Call for Proposals: Real World Engineering Projects
The IEEE is continuing with a second year of funding for a program to develop workshops in IEEE fields of interest for use by faculty members worldwide in electrical engineering (EE), computer engineering (CE), computer science (CS) and electrical engineering technology (EET). The program seeks high quality, online, self-study workshops which will describe the best pedagogical techniques for EE, CE, CS and EET classrooms. The workshops should be based on the latest results from research on learning and techniques to increase student learning in engineering, science, technology and mathematics. Ideally, the workshops will offer practical information that can be easily transferred to the classroom by the faculty who use them. 

Completed workshops will be disseminated by IEEE for use by faculty worldwide to aid in adopting best practices in their classroom. Workshops should address a best pedagogical practice topic from the recent research on learning and provide EE, CE, CS and EET faculty with enough background information and examples to allow them to adopt the best practice in their own classrooms. Authors of completed workshops will receive an honorarium from IEEE. Submissions are open to all faculty members who teach Electrical Engineering, Computer Engineering, Computer Science and/or Electrical Engineering Technology at a university that grants degrees in accredited EE, CE, CS and/or EET programs.  Deadline for abstracts is 15 April 2008. View complete details of the call for proposals or contact the Real World Engineering program at realworldengineering@ieee.org

 
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Chipmaker Debuts 45-NM Sets, Hybrid Graphics
Advanced Micro Devices (AMD) has just launched its 780 Series graphics chipset and first CPUs manufactured with the 45-nanometer process, promising an "additive effect" with the addition of more video cards thanks to its Hybrid Graphics technology. The boards are tailor-made for Microsoft's Vista operating system with support for DirectX 10 and CrossFireX. Paired with an AMD Phenom 9000 series quad-core processor or Athlon 64 X2 dual-core processor, the AMD 780 Series delivers significant enhancements in gaming and high-definition experiences for mainstream PC customers. The firm’s 45-nanometer process (developed with research partner IBM) results in a more efficient fabrication process and prepares the AMD for the eventual shrink to 32-nanometer. According to the firm, the 45nm devices will be commercially available in the second half of 2008. Read more 
Learn more about hybrid graphics in IEEE Xplore®

 
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Chip Makers Tailoring Products for Local Market
As the demand for semiconductors, chips and integrated circuits in India continue to rise because of the increased electronics usage, many companies have initiated India-specific IC programs. Primarily located in Bangalore, which is home to at least 70 percent of the 130 chip design firms operating in the country, the India-specific IC programs incorporate common features, keeping the Indian market in mind to power electronic equipment with an aim to drive down the cost of equipment at the end-user level. According to the India Semiconductor Association (ISA), companies developing India-specific ICs are targeting the top five end-user product categories: mobile handsets, desktops and notebooks, GSM base stations, set top boxes and energy meters. Read more

 
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Circuits and Systems Symposium
The 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008) is being held 18-21 May 2008 in Seattle, Washington, USA. The conference’s theme, “Green Circuits and Systems: Engineering the Environmental Revolution,” will be integrated throughout the conference with a student paper contest, three high profile keynote speeches and quality workshops and tutorials. ISCAS 2008 offers 11 tutorials from worldwide experts in the design of communication transceivers, medical-imaging circuits, microfluidic biochips, synchronization circuits in high-frequency systems and hybrid nano-CMOS circuits. System-oriented tutorials include topics on power electronic modeling, data converters, high-speed data links, sensor networks and MIMO. Learn more

 
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Self-Assembling Organic Circuits Tested
A quick and simple way to make arrays of high-performance electronic devices from organic semiconductor material has been developed by researchers at the National Institute of Standards and Technology (NIST), USA, who say the technology could lead to a simple, low-cost method to manufacture large, flexible electronic circuits. In the process, organic semiconductor molecules self-assemble around chemically pretreated electrodes to form field-effect transistors. This results in an array of transistors with good electrical properties that are insulated from one another. While the technique was demonstrated on a hard silicon substrate, it should be transferable to flexible substrates, researchers say, adding that such circuits could pave the way for roll-up displays, foldable electronic readers, large screens that can be rolled up and tucked into cell phones and smart bandages that monitor wounds and sense the need for drugs. Read more 
Learn more about organic circuits in IEEE Xplore®

 
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Join IEEE for a Free Webinar on Photonic Integrated Circuits
Learn about the latest advancements in photonic integrated circuits in an IEEE webinar taught by IEEE Fellow Christopher R. Doerr. “InP Photonic Integrated Circuits for Fiber-Optic Communications,” scheduled for Wednesday, 9 April 2008 at 2:00 pm EDT, will provide an overview of the technology behind InP PICs, focusing on devices for fiber-optic communications that monolithically integrate two or more functions. Ideal for telecommunications design engineers, research and development engineers and engineering managers, this webinar will highlight how InP-based photonic integrated circuits (PICs) can simplify system designs, reduce space and power consumption, improve reliability and reduce the cost of deploying optical networks.

Christopher R. Doerr earned a B.S. in aeronautical engineering and a B.S., M.S., and Ph.D. in electrical engineering from the Massachusetts Institute of Technology (MIT). Since joining Bell Labs in 1995, Doerr’s research has focused on integrated devices for optical communication. He was promoted to Distinguished Member of Technical Staff in 2000, received the OSA Engineering Excellence Award in 2002, and became an IEEE Fellow in 2006. Doerr is also the Editor-in-Chief of IEEE Photonics Technology Letters.

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IBM and Hitachi Team Up to Advance Chip Research
Technology giants IBM and Hitachi have announced a plan to collaborate on a project aimed at improving semiconductor technology, including shrinking the features on silicon chips. While the research will not apply directly to manufacturing, it is expected to contribute to IBM's manufacturing processes as they relate to future silicon devices. IBM already has a strong profile in advancing semiconductor technology and is developing silicon nano-photonics technology that could replace some of the wires on a chip with pulses of light on tiny optical fibers for quicker and more power-efficient data transfers between cores on a chip. Read more 
Learn more about silicon chips in IEEE Xplore®

 
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E-Noses Sample the Sweet Smell of Success
“Electronic noses,” devices that can detect the chemicals comprising odors, may soon be replacing other technologies in hospitals, public spaces and homes. According to experts, e-nose technology has quietly advanced during the past two decades, including commercial models that can distinguish wines, analyze food flavors and sort lumber. Benchtop systems are also used in the pharmaceutical, food and cosmetics industries, while smaller portable units are used to monitor air quality. Researchers say e-noses currently cost between US$5,000 and US$100,000, but a convergence between e-nose technology and advances in printed electronics will bring e-noses that cost significantly less through the use of conducting polymers. These polymers are sensitive to the chemicals that make up odors and are also capable of producing electrical signals. Researchers are currently investigating ways of using these materials to fabricate ultra low-cost electronics that might let wine bottles monitor the aging of their contents, allow meat packages to flag spoilage and enable mailboxes to check for bombs. Read more 
Learn more about electronic noses in IEEE Xplore®

 
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New Technology for Random Numbers Generated
A physical random-number generation circuit that has the world's highest output by area and generates random numbers at a data rate of 2 Megabits a second has been developed by Toshiba. The random-number generator (RNG) has a circuit size of only 1,200 square micrometers but achieves the level of performance and reliability essential for integration into IC cards and mobile equipment. Toshiba calls the development a major advance in information security technology, saying hacker-proof encryption is essential for secure information transfers in financial transactions and personal information exchanges. Existing cryptographic security technology for IC cards is based on pseudo-RNG algorithms, according to experts, who say the technique is nearing its limitations as network technology advances. The new RNG technology adopts a compact analog-digital converter which effectively amplifies analog noise signals and converts them to digital random numbers. Read more 
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Nano-Printing Technology May Open Way to the Ultra-Small
A new nano-patterning method has been developed by researchers at Seoul National University, who say that by using electron microscopes and lithograph technology, they can create quantum dots and lines that can be used on a 10 nanometers scale or smaller. The Atomic Image Projection Electron-beam Lithography (AIPEL) makes use of natural patterns found in everyday objects, according to researchers, who say if one can see an atomic pattern through an electron microscope, the pattern can be made into a natural mask that can then be carved quickly, cheaply and easily using conventional electron beams and photo resistant materials. Existing technology cannot create circuits in silicon wafers below 25 nanometers, due to the physical limitations of "sculpturing" dots and lines, and this new technology opens the possibility of building of ultra small devices. Read more 
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