|
 |
Find an IEEE Article or Standard in IEEE Xplore digital library  |
|
HELP SPREAD THE WORD ABOUT IEEE
Please
feel welcome to share this with your friends and colleagues.
|
|
Managing Editor: Michelle Garner, whatsnewadmin@ieee.org
SUBSCRIPTION INFORMATION
To subscribe to this or any other What’s New @ IEEE newsletter
please click here.
To modify your current information for What’s New @ IEEE newsletters
please click here.
If you want to subscribe to, or view the archives for, Eye on Washington (USA), click here. |
|
|
 |
Conference Focuses on Nanoscale Era
Sponsored by IEEE, the 2009 International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) will be held in Cairo, Egypt, 6-9 April 2009. The aim of the DTIS conference is to cope with the rapidly progressing electronic technology. The main area of interest for the conference deals with the design, technology and test of electronic products, ranging from integrated circuits, multi-chip modules and printed circuit boards to full systems and microsystems. The conference will also examine the methodologies and tools used in the design and fabrication of such rapidly growing products. Learn more
Reasons for Polymer Film Instability Determined
Imperfections in the forming of polymer films can hinder the performance of potential new technologies, such as solar cells or thin film transistors that employ organic polymer films on their surfaces. According to research chemist Christopher Soles, "If organic photovoltaics—to take just one example—are ever to be realized and marketed, we need to understand how the film formation process works," said Soles. "You have to know the properties of these materials first in order to control their stability." Using model polymers with well understood crystallization behavior, Soles and other scientists from the National Institute for Standards and Technology (NIST) discovered that a few degrees' variation in temperature controls whether crystallization or dewetting (similar to water beading up on a windshield), will dominate the hardening process, thereby granting qualitatively different properties to the finished film. They also determined how localized dewetting might be averted. In addition to improving methods of creating stable crystalline films, the team suggests their research also can offer broader insights. Read more
Learn more about polymer films in the IEEE Xplore® digital library
 BACK TO TOP
Manufacturer and University Join to Explore Use of Neural Network Model
Metal, ceramic or synthetic knitted wire mesh is used in such applications as exhaust systems, sound attenuation, vibration and shock suppression and electromagnetic and radio frequency interference shielding. Welsh manufacturer KnitMesh Technologies is collaborating with Liverpool University on the use of neural networking techniques to improved mesh design, leading to new mesh products. The neural network model is intelligent software that helps predict the performance of knitted mesh components. According to Peter Evans, KnitMesh Technologies general manager, use of a neural network will “bring advanced engineering techniques to the mesh development process, and enable us to develop solutions that meet the widest range of weight, cost and performance objectives in extremely short lead times.” Read more
Learn more about neural networks in the IEEE Xplore® digital library
BACK TO TOP
How to Eliminate "Overqualified" as a Job Search Roadblock
You've searched and searched for a position that matches your skills and experience, but have been unsuccessful in landing one. Now, with your rainy day fund and your unemployment insurance about to dry up, you find yourself eyeing openings a rung or two down the ladder from your previous job. A Monster.com article offers tips for keeping yourself in the running for a job despite hiring managers' unwillingness to consider people who are overqualified. To avoid getting cut down immediately, it suggests withholding your resume until you can make a direct pitch to the hiring manager. This will allow you to describe your employment history in a way tailored to mesh with the job's requirements-emphasizing relevant skills and providing few details about more recent promotions that may cause the employer to fear that he or she will lose you as soon as a better opportunity pops up. Read more
BACK TO TOP
Next-Generation Parallel Circuit Simulator for the Most Challenging Circuit Simulation Tasks Debuts
Cadence Design Systems, Inc. has launched Cadence® Virtuoso® Accelerated Parallel Simulator (APS), its next-generation circuit simulator. A key part of the Cadence Multi-Mode Simulation solution (MMSIM) 7.1 release, the Virtuoso APS was developed to solve the largest and most complex analog and mixed-signal designs across all process nodes. The company reports that new simulator combines proven Cadence simulation technologies and a breakthrough parallel circuit solver, along with a newly architected engine that efficiently harnesses the power of multiprocessing computing platforms. The result is a circuit simulator with an accuracy and use model identical to the Virtuoso Spectre® Circuit Simulator, delivering significantly improved single-thread performance and scalable multi-thread performance. The Virtuoso APS improves convergence and capacity for designs with hundreds of thousands of transistors, reducing design and verification time in most cases from weeks to hours. Helmut Schweiss, director of new business start-ups at ON Semiconductor, said, "The Virtuoso Accelerated Parallel Simulator delivered a 20.6 times performance boost over traditional SPICE simulators, which enabled us to verify and detect multiple design issues, and meet our critical tapeout deadline. This would not have been possible otherwise, and eliminated unwanted surprises during our silicon verification." Read more
Learn more about circuit simulators in the IEEE Xplore® digital library
BACK TO TOP
IEEE Foundation Announces 2009 Grant Deadlines
The IEEE Foundation, the philanthropic arm of the IEEE, is now accepting 2009 grant applications for new and innovative projects. Committed to improving the technological literacy of society from childhood through adulthood, the IEEE Foundation awarded more than US$360,000 in grants during 2008 to projects supporting the advancement of the engineering field. During 2009, unsolicited applications will be accepted from IEEE units and other organizations working in areas of relevance and importance to the IEEE and its membership. Projects should achieve one or more of the following objectives:
* Improve primary and secondary math and science learning
* Increase active interest in engineering and science
* Preserve the history of IEEE-associated technologies
* Tap the technological expertise of IEEE members
Application deadlines:
24 April for June Consideration
11 September for November Consideration
All applications will be considered for funding by the IEEE Foundation Board of Directors. Questions should be directed to the IEEE Foundation Administrator at +1 732 981 3435 or foundation-office@ieee.org. Learn more
BACK TO TOP
DC-DC Converter Simulation Using Substrate Extraction Tool
Portable devices using System-on-chip (SoC) design, which integrates a high frequency switching DC-DC converter directly on the same IC, feature effective power management circuits with reduced bulk and weight. The DC-DC converter introduces large power/ground bounce and substrate noise, however, which can greatly degrade the performance of the analog circuits integrated on the same chip. Traditional circuit simulation methods have not been effective. The Cadence QRC helps to investigate the mechanisms of noise injection for the DC-DC converter and their effects on sensitive analog blocks. It extracts the parasitic resistance and capacitance of the substrate from the layout, and identifies which isolation strategies are effective. QRC has good application for power designs with large power devices. Read more
Learn more about DC-DC Converters in the IEEE Xplore® digital library
BACK TO TOP
Online Seminar to Cover Label Free Sensing with Silicon Nanowires
The Micro and Nano Sensors Interest Group (MiNSIG) of the Sensors and Instrumentation KTN (Knowledge Transfer Network) will hold an online seminar on label free sensing with silicon nanowires on 12 February 2009 at 3:00-4:00 pm GMT (10:00-11:00 am EST). Speaking is Professor Mark Reed, Harold Hodgkinson Chair of Engineering and Applied Science at Yale University and Associate Director of the Yale Institute for Nanoscience and Quantum Engineering. Reed has given 17 plenary and more than 265 invited talks, holds 25 U.S. and foreign patents, and is the recipient of the IEEE Pioneer Award in Nanotechnology (2007), among other awards. The seminar will cover recent developments in nanowire sensors and a novel sensing approach using complementary metal-oxide-semiconductor (CMOS) technology. This approach has achieved unprecedented sensitivity and also facilitates system-scale integration of nanosensors for the first time. The technology enables a wide range of label-free biochemical and macromolecule sensing applications and introduces real-time, unlabeled detection capability. The talk also will discuss specific aspects of microfluidic integration and Debye screening along with a demonstration of live cell peptide-specific immunoresponse. The event is free, but the number of participants is limited and registration is required; those interested should email Tiju Joseph, tiju.joseph@sensorsktn.com. Read more
Learn more about nanowires in the IEEE Xplore® digital library
BACK TO TOP
Nominations Sought for IEEE Awards
Nominees are wanted for the 2010 IEEE medals, awards, recognitions, and prize papers. The deadline for the IEEE Board of Directors to receive nominations is 1 July 2009. Learn more
BACK TO TOP
Read Past What's
New @ IEEE Newsletters 
Search
Issues Prior to May 2007
|
|
|
